1. Field of the Invention
This work addresses the problem of speeding up levelized compiled code generation based functional (delay independent) logic simulation for synchronous digital systems. In particular, the invention relates to methods for manipulation of the netlist to be simulated so that the simulation speed is increased.
2. Description of Related Work
In designing digital systems, it is important to validate the design of the interconnected logic gates. This may be referred to as design validation.
For today's large and complex systems, it is preferred to validate the design by simulation. Design validation by simulation is a key step in the design cycle of digital systems. It is also one of the most time consuming. Each time a design is iterated, it must be re-simulated until a satisfactory confidence level is achieved.
Simulation is performed at various levels of abstraction during the design process. One level of simulation involves delay-independent (i.e. purely functional) cycle-based logic simulation of synchronous digital circuits. At this level, the simulator is required to determine the output sequence produced by a circuit for a sequence of input vectors, independent of the delays associated with the gates and wires. In effect, the simulator determines the output vector for each input vector by evaluating the Boolean equations associated with each gate in the circuit. The circuit is assumed to possess feedback through flip-flops. Therefore, the circuit can be evaluated for the next input vector only after the evaluation for the current input vector is complete. This type of simulation where the input vectors must be simulated sequentially in this is manner is said to be cycle-based sequential simulation.
It will be understood that circuit timing may be checked using static timing analysis. Circuit initialization may be checked using an event driven front end used for simulation of a few thousand cycles. The bulk of the verification tests are done using a pure binary valued functional simulator.
This invention relates particularly to delay-independent (i.e. purely functional) cycle-based logic simulation of synchronous digital circuits. This invention relates, more particularly, to solving the problem that prior simulation methods have been too slow.
Two techniques have traditionally been applied for logic simulation at this level. One technique is event-driven simulation. For their useful background on this topic, the following are incorporated by reference:
M. A. Breuer and A. D. Friedman. Diagnosis and Reliable Design of Digital Systems. Computer Science Press, Inc., 1976. PA1 E. Ulrich. Exclusive simulation of activity in digital networks. In Communications of the ACM, volume 13, pages 102-110, February 1969. PA1 M. Chiang and R. Palkovic. LCC simulators speed development of synchronous hardware. In Computer Design, pages 87-91, 1986. PA1 N. Ishiura, H. Yasuura, T. Kawata, and S. Yajima. High-speed logic simulation on a vector processor. In Proceedings of the International Conference on Computer-Aided Design, pages 119-121, November 1985. PA1 G. F. Pfister. The Yorktown Simulation Engine: Introduction. In The Proceedings of the Design Automation Conference, pages 51-54, June 1982. PA1 L. T. Wang, N. H. Hoover, E. H. Porter, and J. J. Zasio. SSIM: A software levelized compiled-code simulator. In The Proceedings of the Design Automation Conference, pages 2-8, June 1987. PA1 E. J. Shriver and K. A. Sakallah. Ravel: Assigned-delay compiled-code logic simulation. In Proceedings of the International Conference on Computer-Aided Design, pages 364-368, November 1992. PA1 the use of sweep, eliminate and factor to reduce number of literals; PA1 use of cofactoring for speeding up simulation; PA1 register allocation and spill scheme; PA1 inverter minimization scheme; PA1 shift minimization scheme; and PA1 retiming for simulation speed--for compiled code simulation in general.
The other to the two techniques traditionally applied for logic simulation at this level is levelized compiled-code (LCC) simulation. The following, which are incorporated by reference, provide useful background on prior efforts in LCC simulation:
FIG. 1 presents a high-level view of how these simulators are used. It has been observed in practice that levelized compiled-code simulation is much faster than event driven simulation for purely functional simulation of current designs.